TCP (Tape Carrier Package) type semiconductor apparatuses (hereinafter, “TCP semiconductor apparatus”) have conventionally been known as semiconductor apparatuses in which a semiconductor device is mounted on and coupled to a flexible printed circuit.
In recent years, COF type semiconductor apparatuses (hereinafter, “COF semiconductor apparatus) have been employed. In the COF semiconductor apparatus, a semiconductor device is mounted on and coupled to a flexible printed circuit by use of the COF method.
The following are exemplary differences between the TCP semiconductor apparatuses and the COF semiconductor apparatuses.
(i) In the TCP semiconductor apparatus, an opening section is made in advance in an insulating tape used as a base substrate of a flexible printed circuit. The opening section is utilized to mount a semiconductor device. A wiring pattern is formed in the opening section so as to protrude in the shape of a cantilever. A top end section of the wiring pattern is coupled to the semiconductor device. On the other hand, in the COF semiconductor apparatus, a thin film of an insulating tape, which is used as a base substrate in a flexible printed circuit, has no opening section to be utilized to mount a semiconductor device. The semiconductor device is mounted on and coupled to a wiring pattern formed on a front surface of the thin film of the insulating tape.
(ii) In the TCP semiconductor apparatus, the wiring pattern protrudes in the shape of a cantilever. This makes it difficult to produce a wiring pattern with a wiring pitch smaller than 45 μm. On the other hand, in the COF semiconductor apparatus, the wiring pattern is formed on the front surface of the thin film of the insulating tape. It is therefore easy to produce a wiring pattern with a wiring pitch of 35 μm or smaller.
(iii) The TCP semiconductor apparatus includes a slit along which the TCP semiconductor apparatus is to be folded after being mounted on a liquid crystal panel or the like. On the other hand, the COF semiconductor apparatus has no such slit. The COF semiconductor apparatus can be folded along any line of the thin film of the insulating tape.
(iv) The TCP semiconductor apparatus is produced by adhering, with a bonding agent, a copper foil to an insulating tape made of polyimide. On the other hand, the COF semiconductor apparatus is produced by applying polyimide or the like to a rear surface of a copper foil and then carrying out hardening to form the shape (casting). Alternatively, the COF semiconductor apparatus is produced by carrying out sputtering to form a layer of copper on the thin film of an insulating tape made of polyimide or the like (sputtering, metalizing).
As described above, in view of purposes of use, the COF semiconductor apparatus employs, as the base substrate in the flexible printed circuit, the thin film of the insulating tape that can be folded freely. Respective wirings of the wiring pattern provided on the front surface of the thin film of the insulating tape are electrically connected to corresponding terminals of the semiconductor device. A connector section for external connection is connected to a liquid crystal panel, a printed wiring board, and the like. Solder resist is applied to the remaining revealed part of the wiring pattern other than those mentioned above, thereby keeping the remaining revealed part insulated.
It is easier with the COF semiconductor apparatus to realize a finer pitch of the wiring pattern (inner lead) than with the TCP semiconductor apparatus. A lower limit of the wiring pitch in mass-produced TCP semiconductor apparatuses is 45 μm. On the other hand, mass production of COF semiconductor apparatuses with the wiring pitch of 35 μm has been carried out. With the COF semiconductor apparatuses, it is possible to realize a wiring pitch of 30 μm or smaller.
The COF semiconductor apparatuses have been demanded to be responsive to multi-pins, and at the same time, to become smaller and thinner. To meet the demands, the following are necessary. First, a pitch of the sections connecting the wiring patterns and the semiconductor devices needs to be finer. Further, a pitch of the connector sections of the wiring pattern for external connection needs to be finer. Furthermore, insulating tapes, wiring patterns, and the like need to be thinner. To make the pitches of the wiring patterns (inner lead) finer, the width and the thickness of the wiring patterns (inner lead) need to be reduced.
FIGS. 5 and 6 each show a schematic structure of the vicinity of a mount section (mount area) of a semiconductor device in a conventional general COF semiconductor apparatus. FIG. 5 shows a case in which the wiring pitch of the wiring pattern is 35 μm or greater. FIG. 6 shows a case in which the wiring pitch of the wiring pattern is smaller than 35 μm (in this case, the wiring pitch is finer than that in the case shown in FIG. 5). Hereinafter, the conventional case shown in FIG. 5 will be referred to as “conventional apparatus 1”, and the conventional case shown in FIG. 6 will be referred to as “conventional apparatus 2”.
As shown in FIGS. 5 and 6, the wiring pattern 23 in a flexible printed circuit for a conventional general COF semiconductor apparatus is formed in such a manner that a part of the wiring pattern 23, which part is indicated by the dashed double-dotted lines in FIGS. 5 and 6 and is to be connected to the bump electrode 25 of the semiconductor device 24, and the remaining part of the wiring pattern 23 have a same width (wiring width).
On the other hand, Patent Document 1 (U.S. Pat. No. 3,536,023; Date of Registration: Mar. 19, 2004; Date of Issue: Jun. 7, 2004) describes a known technique in which a width of a wiring pattern is partially changed. FIG. 7 shows a schematic structure of the vicinity of a mount section (mount area) of a semiconductor device in the COF semiconductor apparatus (hereinafter, “conventional apparatus 3”) disclosed in Patent Document 1.
As shown in FIG. 7, in the conventional apparatus 3, the wiring pattern 23 is formed so as to have a wide width in the vicinity of an edge of the opening section 22a of the solder resist 22. The wiring pattern 23 has the same width throughout the overlap part (i.e. part on which the semiconductor device 24 is to be mounted), which is indicated by the dashed double-dotted line and overlaps the semiconductor device 24, including a part to be connected to the bump electrode 25 of the semiconductor device 24 and the remaining part of the wiring pattern 23.
As mentioned above, there have been demands for COF semiconductor apparatuses with wiring patterns having finer pitches, thinner films of insulating tapes, and thinner films of wiring patterns. There are, however, several obstacles in realizing finer pitches and thinner films.
One of the obstacles is that, because the pitch of the wiring pattern (inner lead) is small, a defect occurs if the bump electrode of the semiconductor device is displaced when bonded to the wiring pattern (inner lead). Specifically, the wiring pattern (inner lead) comes into contact with an adjacent bump electrode to the bump electrode.
In other words, in a COF semiconductor apparatus with a fine wiring pitch smaller than 35 μm, if the bump electrode of the semiconductor device is displaced when bonded to the wiring pattern, the defect is likely to occur that the wiring pattern (inner lead) comes into contact with an adjacent bump electrode to the bump electrode. This problem is more likely to occur in a COF semiconductor apparatus with a wiring pitch of 30 μm or smaller.
One way to overcome the obstacles is to narrow the wiring pattern (inner lead). This prevents the defect even if the bump electrode of the semiconductor device is displaced when bonded to the wiring pattern. Specifically, the wiring pattern is prevented from coming into contact with an adjacent bump electrode to the bump electrode. However, narrowing the width of the wiring pattern (inner lead) results in degrading mechanical strength of the wiring pattern and bond strength between the wiring pattern and the insulating tape. This causes a problem that the wiring pattern is easily disconnected or easily peels off in the steps from mounting and bonding the semiconductor device to packaging the COF semiconductor apparatus into a module.
The COF semiconductor apparatus can be folded freely. There is, however, difficulty in realizing a finer pitch while maintaining this characteristic of the COF semiconductor apparatus, that is, the COF semiconductor apparatus can be folded freely. Specifically, folding the COF semiconductor apparatus freely causes the wiring pattern to be easily disconnected or to peel off easily. Therefore, the wiring pattern (inner lead) having been made finer needs to improve in mechanical strength and bond strength.
The following describes the foregoing obstacles, with reference to the conventional apparatus 1 and the conventional apparatus 2.
FIG. 8 schematically shows a structure of the connecting section, via which the semiconductor device 24 is connected to the wiring pattern 23, in the COF semiconductor apparatus shown in FIG. 5 (conventional apparatus 1), in the case in which the bump electrode 25 of the semiconductor device 24 is displaced when bonded to the wiring pattern 23. FIG. 9 schematically shows a structure of the connecting section, via which the semiconductor device 24 is connected to the wiring pattern 23, in the COF semiconductor apparatus (conventional apparatus 2) shown in FIG. 6, in the case in which the bump electrode 25 of the semiconductor device 24 is displaced when bonded to the wiring pattern 23. FIG. 8 shows a structure in part B shown in FIG. 5. FIG. 9 shows a structure in part C shown in FIG. 6.
As shown in FIG. 8, the wiring pitch is wide in the conventional apparatus 1. Therefore, even if the bump electrode 25 is displaced when bonded to the wiring pattern 23, the defect is less likely to occur that the wiring pattern 23 comes into contact with an adjacent bump electrode to the bump electrode 25. Thus, even if the bump electrode 25 is displaced when bonded to the wiring pattern 23, the wiring pattern 23 and the bump electrode 25 are electrically connected in a suitable manner.
With the conventional apparatus 2, the defect is more likely to occur. Specifically, if the bump electrode 25 is displaced when bonded to the wiring pattern 23, the wiring pattern 23 comes into contact with an adjacent bump electrode 25 to the bump electrode 25, as shown in FIG. 6.
As described above, one way to overcome the defect mentioned above is to reduce the width of the wiring pattern 23 along with reducing the pitch of the wiring pattern 23.
FIG. 10 shows a COF semiconductor apparatus (hereinafter, “conventional apparatus 4”) in which the width of the wiring pattern 23 is smaller than that of the wiring pattern 23 employed in the conventional apparatus 2 shown in FIG. 6.
As shown in FIG. 10, with the conventional apparatus 4, the defect is prevented even if the bump electrode 25 is displaced when connected to the wiring pattern 23 in the case in which the wiring pitch is reduced. Specifically, the wiring pattern 23 is prevented from coming into contact with an adjacent bump electrode 25 to the bump electrode 25.
However, narrowing the width of the wiring pattern 23 as shown in FIG. 10 results in degrading mechanical strength of the wiring pattern 23 and bond strength between the wiring pattern 23 and the insulating tape 21. This causes a problem that the wiring pattern 23 is disconnected or peels off.
FIG. 7 shows the invention disclosed in Patent Document 1 (conventional apparatus 3). According to Patent Document 1, in order to prevent disconnection of the wiring pattern 23 in the vicinity of the opening section 22a of the solder resist 22, which disconnection is likely to occur when different temperatures are applied repeatedly, the width (wiring width) of the wiring pattern 23 is greater in the vicinity of an edge of the opening section 22a of the solder resist 22 than in the connecting section (inner lead section) that electrically connects the wiring pattern 23 and the semiconductor device 24. Patent Document 1 makes, however, no particular mention of the width of the wiring pattern 23 in the inner lead section.